Analog-to-digital converters (AD converters) are roughly classified into three types of a successive-approximation type, a parallel comparison type, and a delta sigma (ΔΣ) type. Of these, the parallel comparison type is also called a flash type, and can obtain a digital value in a single comparison using (2n−1) comparative voltages and (2n−1) comparators for dividing a full scale of the analog signal into 2n sections. For this reason, a parallel comparison type AD converter operates at highest speed.
However, the parallel comparison type is known to have a problem that a circuit size is large. The reason is as follows. An AD converter includes three basic elements of a resistor ladder for generating a comparative voltage, a comparator group, and an encoder. The conversion accuracy of the AD converter is determined depending on the accuracy of the resistor ladder and the resolution of the comparator, and the accuracy or the resolution is improved as the circuit area increases.
That is, in the parallel comparison type, the circuit size increases in exchange for an improvement in the conversion accuracy. In other words, it is difficult to achieve high resolution with a small circuit area.
Here, the comparator includes a differential pair for detecting a potential difference between two inputs, and in order to achieve high resolution, a variation in a threshold value of input transistors forming the differential pair needs to be suppressed. The accuracy of the threshold value differs according to a generation of a CMOS fabrication technique, and it is desirable to use a higher-level technique. Thus, the number of bits of the resolution of the parallel comparison type AD converter is basically limited to the range of accuracy of semiconductor microfabrication technique, and the circuit area and the resolution are in a trade-off relation.